1. Field of the Invention
The present invention relates to a MOS transistor and a manufacturing method thereof by which a short channel phenomenon caused by miniaturization of the device is suppressed and high speed operation can be maintained.
2. Description of the Prior Art
With accelerated improvements in semiconductor manufacturing processes, devices such as MOS transistors have become miniaturized to on the order of a quarter micron in size. As a result, certain phenomena, including a short channel effect, can alter performance of devices.
The short channel effect refers to the reduction in transistor threshold voltage with reduced channel length. The threshold voltage of a small-sized transistor, i.e., channel length less than 0.4 .mu.m, decreases exponentially with decreasing channel length. The effect occurs because a shorter channel has a relatively larger portion of its active region affected by the drain voltage as compared to the portion under the influence of the gate voltage. The effect may be mitigated somewhat by defining the minimum transistor size to be larger than the size of the transistor having the minimally acceptable voltage threshold characteristics.
The short channel effect can be interpreted with a one-dimensional charge sharing model. Also, an accurate model for interpretting the short channel effect has been realized with numerical value analysis according to two-dimensional potential barrier lowering.
Various approaches to mitigating the short channel effect have been realized. For example, the thickness of the gate oxide layer, the maximum width of the depletion layer below the gate and the dopant density of the substrate can be decreased. Also, it is important to form a shallow junction to inhibit the effect.
Accordingly, a shallow ion implantation approach was introduced in the field of ultra large-scale integration (ULSI). Also, shallow junctions can be realized by using a rapid thermal annealing (RTA) process for heat treatment. As a result of these techniques, the short channel MOS transistor is taking preliminary steps to its introduction into mass production.
However, in spite of the introduction of the techniques for forming the shallow junction, the conventional techniques for the shallow junction are considered to have approached the limits of their applicability to high density, high integration devices in mass production, particularly as devices sizes approach a quarter-micron.
The conventional MOS transistor is generally modeled with a lightly doped drain (LDD) structure. Such an LDD structure is deposited on a moderate doped drain (MDD) in a shallow junction structure. The MDD structure compared with the LDD structure has enhanced the performance of the device by widenning a dopant level of the LDD region from 1.times.10.sup.14 /cm.sup.2 to 1.times.10.sup.15 /cm.sup.2. However, there is a problem in that the short channel effect according to short-channelization is mainly caused by the enhancement of the doping level in the MDD region.